The present invention relates to a semiconductor device, and more particularly to a CMOS device with an improved lightly doped drain structure suppressing hot carriers, which allows the CMOS device to exhibit high performance and to be scaled down, as well as a method of forming the same.
As the MOS field effect transistor has been scaled down, serious problems are raised with deterioration of performance of the MOS field effect transistor due to hot carrier injection and also with leakage of current between a source and a drain of the MOS field effect transistor due to short channel effects.
In order to avoid the deterioration of the performance due to the hot carrier injections, it is effective to relax the electric field in the vicinity of the drain of the MOS field effect transistor. In order to relax the electric field, it is effective to form a lightly doped drain structure of the MOS field effect transistor.
On the other hand, the leakage of current between the source and drain of the MOS field effect transistor is caused by punch through phenomenons. The punch through phenomenons are caused by the fact that the space charge regions of the source and drain regions are made adjacent to each other.
The MOS field effect transistors usually have a double-layered structure like a gate electrode that comprises an n-type polysilicon layer or a double layered structure of an n-type polysilicon layer and a metal suicide layer. In this case, an n-channel MOS field effect transistor is a surface channel MOS field effect transistor, whilst a p-channel MOS field effect transistor is a buried channel MOS field effect transistor. A remarkable leakage of current between source and drain regions due to the punch through phenomenon may appear in the buried p-channel MOS field effect transistor. However, the buried p-channel MOS field effect transistor has a sufficient distance between a channel region and a gate oxide film for preventing hot carriers from being injected into the gate oxide film, for which reason the buried p-channel MOS field effect transistor reduces the deterioration of the performance due to the hot carrier injection into the oxide film.
In order to settle the above problem with the source-drain current leakage due to the punch through phenomenon, it is effective to form punch through stopper regions under the lightly doped drain p-type diffusion layers of the p-channel MOS field effect transistor. The following descriptions will focus on the p-channel MOS field effect transistor with the punch through stopper regions under the lightly doped drain p-type diffusion layers. FIG. 1 is a fragmentary cross sectional elevation view illustrative of a conventional CMOS device including a p-channel MOS field effect transistor with punch through stopper regions. The CMOS device is formed on a p-channel semiconductor substrate 10. Field oxide films 20 having a thickness of about 300-500 nanometers are selectively formed over a surface of the p-channel semiconductor substrate 10 to define active regions of the p-channel semiconductor substrate 10. Further, a p-type impurity such as boron is selectively ion-implanted into regions under the field oxide films 20 thereby forming p-type channel stoppers 21. A p-well region 11 and an n-well region 12 are formed in an upper region of the p-channel semiconductor substrate 10. The p-well region 11 is selectively formed by a selective ion-implantation of a p-type impurity such as boron into the p-channel semiconductor substrate 10 and a subsequent heat treatment at a temperature of 1000-1200.degree. C. in a nitrogen atmosphere for 30-60 minutes. On the other hand, the n-well region 12 is selectively formed by a selective ion-implantation of an n-type impurity such as phosphorus or arsenic into the p-channel semiconductor substrate 10 and the above subsequent heat treatment.
A gate oxide film 30 having a thickness of about 6-10 nanometers is formed which extends over the p-well region 11 and the n-well region 12 as well as over the field oxide films 20. A heavily doped n+-type polysilicon layer 32 is entirely formed which extends over the gate oxide film 30. Further, a metal silicide layer 33 such as a tungsten silicide layer is formed which extends over the heavily doped n+-type polysilicon layer 32. The laminations of the heavily doped n+-type polysilicon layer 32 and the metal silicide layer 33 are patterned by a photo-lithography technique to thereby form gate electrodes 31 which comprise the laminations of the heavily doped n+-type polysilicon layer 32 and the metal silicide layer 33. An n-type impurity such as phosphorus or arsenic is selectively ion-implanted into the p-well region 11 by use of the gate electrode 31 and the field oxide films 20 as masks whereby lightly doped drain n--type diffusion layers 41 are formed in the p-well region 11. A p-type impurity such as boron or boron fluoride is also selectively ion-implanted into the n-well region 12 by use of the gate electrode 31 and the field oxide films 20 as masks whereby lightly doped drain p--type diffusion layers 42 are formed in the n-well region 12. Further, an n-type impurity such as phosphorus or arsenic is selectively ion-implanted into the n-well region 12 and under the lightly doped drain p--type diffusion layers 42 but only in the vicinity of a channel region defined between the lightly doped drain p--type diffusion layers 42 whereby punch through stopper regions 43 are selectively formed in the n-well region 12 and under the lightly doped drain p--type diffusion layers 42 but only in the vicinity of a channel region defined between the lightly doped drain p--type diffusion layers 42.
A silicon oxide film is entirely formed which extends over the gate electrodes 31, the lightly doped drain n--type diffusion layers 41, and the lightly doped drain p--type diffusion layers 42 as well as the field oxide films 20. The silicon oxide film is then subjected to an etch back to selectively form side wall oxide films 50 on side walls of the gate electrodes 31.
An n-type impurity such as phosphorus and arsenic is selectively ion-implanted into the p-well region 11 by use of the field oxide films 20, the gate electrode 31 and the side wall oxide films 50 as masks to selectively form source/drain n+-type diffusion layers 61 in the p-well region 11. A p-type impurity such as boron is selectively ion-implanted into the n-well region 12 by use of the field oxide films 20, the gate electrode 31 and the side wall oxide films 50 as masks to selectively form source/drain p+-type diffusion layers 62 in the p-well region 12. As a result, an n-channel MOS field effect transistor is formed in the p-well region 11, whilst a p-channel MOS field effect transistor is formed in the n-well region 12.
As described above, the conventional CMOS device has the punch through stoppers 43 in the n-well region 12 and under the side wall oxide films 50 in order to prevent the punch through of the p-channel MOS field effect transistor or prevent leakage of current between the source and drain regions of the p-channel MOS field effect transistor.
Since, however, boron as the p-type impurity has a large diffusion constant in silicon, the p-type diffusion layers such as the lightly doped drain layers 42 and the source and drain diffusion layers 62 show large diffusion in a lateral direction. For this reason, it is required to provide a large width of the side walls so as to prevent the n-type diffusion layers that serve as the punch through stoppers from being captured by or overlapped by the p-type diffusion layers whereby the punch through stoppers can no longer exhibit those function for preventing the punch through between the source and drain.
The side walls of the n-channel and p-channel MOS field effect transistors selectively formed in the p-well and n-well regions 11 and 12 are made from a single silicon oxide film through the etch back process, for which reason the side walls of the n-channel and p-channel MOS field effect transistors have the same width. In order to ensure the sufficiently large punch through stoppers, it is required to provide a large width of the side walls of the p-channel MOS field effect transistor in the n-well region 12. This means that the side walls of the n-channel MOS field effect transistor in the p-well region 11 also have the same large width as the side walls of the p-channel MOS field effect transistor in the n-well region 12. Further, a length of the lightly doped drain n--type diffusion layers 41 are substantially the same as the side walls of the n-channel MOS field effect transistor in the p-well region 11. This means that the lightly doped drain n--type diffusion layers also have a long length. The enlargement in length of the lightly doped drain n--type diffusion layers 41 of the n-channel MOS field effect transistor in the p-well region 11 causes an increase in parasitic capacitance of the n-channel MOS field effect transistor. The increase in parasitic capacitance of the n-channel MOS field effect transistor results in a reduction of driving power.
For the above conventional CMOS device, it is difficult to obtain both the p-channel MOS field effect transistor which is capable of preventing the punch through and the n-channel MOS field effect transistor which has a large driving power.
In order to settle the above problems, a second conventional CMOS device has been proposed which is disclosed in Japanese laid-open patent publication No. 7-183390. This second conventional CMOS device will be described with reference to FIG. 2. FIG. 2 is a fragmentary cross sectional elevation view illustrative of another conventional CMOS device including a p-channel MOS field effect transistor with punch through stopper regions. The CMOS device is formed on a p-channel semiconductor substrate 10. Field oxide films 20 having a thickness of about 300-500 nanometers are selectively formed over a surface of the p-channel semiconductor substrate 10 to define active regions of the p-channel semiconductor substrate 10. Further, a p-type impurity such as boron is selectively ion-implanted into regions under the field oxide films 20 thereby forming p-type channel stoppers 21. A p-well region 11 and an n-well region 12 are formed in an upper region of the p-channel semiconductor substrate 10. The p-well region 11 is selectively formed by a selective ion-implantation of a p-type impurity such as boron into the p-channel semiconductor substrate 10 and a subsequent heat treatment at a temperature of 1000-1200.degree. C. in a nitrogen atmosphere for 30-60 minutes. On the other hand, the n-well region 12 is selectively formed by a selective ion-implantation of an n-type impurity such as phosphorus or arsenic into the p-channel semiconductor substrate 10 and the above subsequent heat treatment.
A gate oxide film 30 having a thickness of about 6-10 nanometers is formed which extends over the p-well region 11 and the n-well region 12 as well as over the field oxide films 20. A heavily doped n+-type polysilicon layer 32 is entirely formed which extends over the gate oxide film 30. Further, a metal suicide layer 33 such as a tungsten silicide layer is formed which extends over the heavily doped n+-type polysilicon layer 32. The laminations of the heavily doped n+-type polysilicon layer 32 and the metal silicide layer 33 are patterned by a photo-lithography technique to thereby form gate electrodes 31 which comprise the laminations of the heavily doped n+-type polysilicon layer 32 and the metal suicide layer 33. An n-type impurity such as phosphorus or arsenic is selectively ion-implanted into the p-well region 11 by use of the gate electrode 31 and the field oxide films 20 as masks whereby lightly doped drain n--type diffusion layers 41 are formed in the p-well region 11. A p-type impurity such as boron or boron fluoride is also selectively ion-implanted into the n-well region 12 by use of the gate electrode 31 and the field oxide films 20 as masks whereby lightly doped drain p--type diffusion layers 42 are formed in the n-well region 12. Further, an n-type impurity such as phosphorus or arsenic is selectively ion-implanted into the n-well region 12 and under the lightly doped drain p--type diffusion layers 42 but only in the vicinity of a channel region defined between the lightly doped drain p--type diffusion layers 42 whereby punch through stopper regions 43 are selectively formed in the n-well region 12 and under the lightly doped drain p--type diffusion layers 42 but only in the vicinity of a channel region defined between the lightly doped drain p--type diffusion layers 42.
A silicon oxide film is entirely formed which extends over the gate electrodes 31, the lightly doped drain n--type diffusion layers 41, and the lightly doped drain p--type diffusion layers 42 as well as the field oxide films 20. The silicon oxide film is then subjected to an etch back to selectively form first side wall oxide films 51 on side walls of the gate electrodes 31.
An n-type impurity such as phosphorus and arsenic is selectively ion-implanted into the p-well region 11 by use of the field oxide films 20, the gate electrode 31 and the first side wall oxide films 51 as masks to selectively form source/drain n+-type diffusion layers 61 in the p-well region 11.
A second oxide film is entirely formed which extends over the first side wall oxide films 51, the gate electrodes 31, the lightly doped drain n--type diffusion layers 41, and the lightly doped drain p--type diffusion layers 42 as well as the field oxide films 20. The second silicon oxide film is then subjected to an etch back to selectively form second side wall oxide films 52 on the first side wall oxide films 51 whereby gate side walls 50 are formed on the opposite side walls of the gate electrodes 31 which comprise the first and second side wall oxide films 51 and 52.
A p-type impurity such as boron or boron fluoride is selectively ion-implanted into the n-well region 12 by use of the field oxide films 20, the gate electrode 31 and the side wall oxide films 50 as masks to selectively form source/drain p+-type diffusion layers 62 in the p-well region 12. As a result, an n-channel MOS field effect transistor is formed in the p-well region 11, whilst a p-channel MOS field effect transistor is formed in the n-well region 12.
The side walls of the n-channel and p-channel MOS field effect transistors selectively formed in the p-well and n-well regions 11 and 12 comprise double layered silicon oxide films 51 and 52. Namely, a length of the lightly doped drain n--type diffusion layers 41 is substantially the same as the thickness of the first side wall oxide film 51 whilst the punch through stoppers 43 has substantially the same width as the total thickness of the first and second side wall oxide films 51 and 52. This means that the lightly doped drain n--type diffusion layers are allowed to be reduced in length, even the punch through stoppers 43 have a sufficiently large width for preventing the punch through. The reduction in length of the lightly doped drain n--type diffusion layers 41 of the n-channel MOS field effect transistor in the p-well region 11 causes a reduction in parasitic capacitance of the n-channel MOS field effect transistor. The reduction in parasitic capacitance of the n-channel MOS field effect transistor allows an increase of driving power.
Of the advanced MOS field effect transistors, the n-channel MOS field effect transistor has a gate which comprises a double layered structure of an n-doped polysilicon layer and a metal silicide layer. On the other hand, the p-channel MOS field effect transistor has a gate which comprises a double layered structure of a p-doped polysilicon layer and a metal silicide layer. For those reasons, both the n-channel and p-channel MOS field effect transistors are of the surface channel type.
The surface p-channel MOS field effect transistor may reduce the short channel effects remarkably as compared to the conventional buried p-channel MOS field effect transistor. In the buried p-channel MOS field effect transistor, the channel region is formed which is positioned just deeper than the interface between the gate oxide film and the silicon substrate, for which reason the p-type impurity such as boron is required to be ion-implanted deeply thereby resulting in an enlargement in lateral diffusion of the p-type impurity. This enlargement in lateral diffusion of the p-type impurity causes a remarkable short channel effect.
By contrast, in the surface channel type MOS field effect transistor, the channel region is formed in the vicinity of the interface between the gate oxide film and the silicon substrate, for which reason the lightly doped drain p--type diffusion layers and the source/drain p+-type diffusion layers are formed shallow in the vicinity of the surface of the semiconductor substrate, for which reason a lateral diffusion of boron is somewhat suppressed. As a result, the short channel effect is suppressed.
The shallow diffusion layers and the short-distance diffusion of the p-type impurity allows shortening the lightly doped drain regions because the punch through stopper regions are not overlapped or captured by the lightly doped drain layers and the source/drain diffusion layers.
Of the surface channel MOS field effect transistors, both the p-channel and n-channel MOS field effect transistors are more concerned with the problem in characteristic deterioration due to the hot carriers rather than the short channel effects. Such characteristic deterioration due to the hot carriers is remarkable as the field concentration of the transistor is increased by scaling down the transistor.
The carrier of the n-channel MOS field effect transistor is electron, whilst the carrier of the p-channel MOS field effect transistor is hole. Since electron is much smaller in mass than hole, electron injection is caused at a higher speed than hole injection under the same electric field. Namely, if the field relaxation at the lightly doped drain regions is almost the same between the n-channel and p-channel MOS field effect transistors, the probability of causing the hot carrier in the n-channel MOS field effect transistor is higher than that of the p-channel MOS field effect transistor. This means that in order to provide the n-channel and p-channel MOS field effect transistors with the same resistively to the hot carrier, it is required to largely relax the field concentration at the lightly doped drain region of the n-channel MOS field effect transistor as compared to the p-channel MOS field effect transistor.
The intensity of the field at the lightly doped drain region is defined by a gradient of the impurity concentration profile over the lightly doped drain region, for which reason it is required that the n-channel MOS field effect transistor has a larger gradient of the impurity concentration profile over the lightly doped drain region as compared to the p-channel MOS field effect transistor. It is therefore required to ensure a large length of the lightly doped drain layer.
Consequently, the first conventional CMOS device has the problem that since the side walls of the n-channel and p-channel MOS field effect transistors are the same, then it is difficult to obtain both the sufficiently wide punch through layers of the p-channel MOS field effect transistor for preventing the punch through and the shortened lightly doped drain layers of the n-channel MOS field effect transistors for reduction in parasitic capacitance to improve the driving ability.
The second conventional CMOS device has the problem that the p-channel MOS field effect transistor has the long size lightly doped drain layer whereby the driving power is deteriorated.
Accordingly, of the first and second conventional CMOS devices, it is difficult to obtain both the sufficiently wide punch through layers of the p-channel MOS field effect transistor for preventing the punch through and the shortened lightly doped drain layers of the n-channel MOS field effect transistors for reduction in parasitic capacitance to improve the driving ability.
In the above circumstances, it had been required to develop a novel CMOS device having sufficiently wide punch through layers of the p-channel MOS field effect transistor for preventing the punch through and sufficiently shortened lightly doped drain layers of the n-channel MOS field effect transistors for reduction in parasitic capacitance to improve the driving ability for high speed performance.